sct63240规格书20W无线充全桥驱动芯片-骊微电子.pdf
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1、SCT63240 Preliminary Datasheet - Revised Aug. 2018 For more information 2018Silicon Content Technology Co., Ltd. All Rights Reserved SILICONCONTENT TECHNOLOGY 20W High-Integration, High-Efficiency Power Solution for Wireless Power Transmitter FEATURES Input Voltage Range: 4V-16V Up to 20W Power Tran
2、sfer Integrated High Efficiency Full-Bridge Power Stage Integrated High Efficiency 5V-1A Buck Convertor Optimized for EMI Build in 3.3V-200mA LDO Provide 2.5V Voltage Reference Integrated Input Current sense with 2% accuracy for FOD and modulation 3.3V and 5V PWM Signal compatible Input Under-Voltag
3、e Lockout Over current protection Thermal shutdown 3mm*4mm QFN-19L Package Friendly for PCB layout APPLICATIONS WPC Compliant Wireless Chargers of 7.5W to 15W Systems for Mobiles, Tablets and Wearable devices General Wireless Power Transmitters for Consumer, Industrial and Medical Equipment Propriet
4、ary Wireless Chargers and Transmitters DESCRIPTION The SCT63240 is a highly integrated power solution optimized for wireless power transmitter applications. This product can be combined with a specialized controller or general MCU based transmitter controller to achieve high performance, high effici
5、ent and cost effective wireless power transmitter system which compliant with WPC specification. This device integrates all the power functions in a wireless power transmitter including Full bridge power stage,5V Buck converter, 3.3V LDO and input current sensing to simplify system design and minimi
6、ze external components thus improve system efficiency. The integrated Full bridge supports up to 20W power transfer and ensures efficient switching with EMI emission. The build in 5V buck convertor and 3.3V LDO provide power rails to transmitter controller and external equipment and also the power s
7、tage driver inside. The build in current detection circuits provides input current information with 2% accuracy to support FOD(Foreign Object Detection) and current modulation. The SCT63240 has built-in protection features including input under-voltage lockout, power stage over current protection an
8、d short-circuit protection, and thermal shutdown protection. The SCT63240 is available in an 19-pin flip chip QFN 3mm*4mm package. TYPICAL APPLICATION BST1 SW1 BST1 SW1 SW2SW2 BST2 PGND BST3 BST2 PGND BST3 SW3SW3 VDD PWM1 PWM2 ISNS PVIN1 VDD PWM1 PWM2 ISNS PVIN1 PGND PVIN2 PGND PVIN2 SCT63240SCT6324
9、0 V3P3V3P3 ENEN GND VIN GND VIN AGND VREF AGND VREF 45.00% 50.00% 55.00% 60.00% 65.00% 70.00% 75.00% 80.00% 85.00% 90.00% 00.20.40.60.81 Efficiency(%) RX Output Current(A) 5W 10W 现货TEL:13808858392 杜S SCT63240 2For more information 2018Silicon Content Technology Co., Ltd. All Rights Reserved DEVICE O
10、RDER INFORMATION PART NUMBER PACKAGE MARKING PACKAGE DISCRIPTION SCT63240FIAR 63240 QFN-19L ABSOLUTE MAXIMUM RATINGS Over operating free-air temperature unless otherwise noted (1) PIN CONFIGURATION DESCRIPTION MIN MAX UNIT BSTBST1 1 SWSW1 1 SWSW2 2 BSTBST2 2 PGNDPGND BSTBST3 3SWSW3 3VDDVDD PWMPWM1 1
11、PWMPWM2 2ISNSISNS PVINPVIN1 1 PVINPVIN2 2 ENEN GNDGNDVINVIN AGNDAGNDVREFVREF V V3 3P P3 3 1 1 2 2 3 3 4 45 56 67 78 89 9 1010 1111 1212 1313 1414151516161717 18181919 Figure 1. Top view 19-Lead QFN 3mm*4mm VIN -0.3 24 V PVIN1, PVIN2 -0.3 19 V SW1,SW2 -1 19 V SW3 -1 24 V BST1,BST2 -0.3 25 V BST3 -0.3
12、 30 V BST1-SW1,BST2-SW2,BST3-SW3 -0.3 6 V VDD, V3P3, VREF, ISNS, EN, PWM1, PWM2 -0.3 6 V Operating junction temperature TJ-40 (2) 125 C Storage temperature TSTG -65 150 C (1) Stresses beyond those listed under Absolute Maximum Rating may cause device permanent damage. The device is not guaranteed to
13、 function outside of its Recommended Operation Conditions. (2) The IC includes over temperature protection to protect the device during overload conditions. Junction temperature will exceed 150C when over temperature protection is active. Continuous operation above the specified maximum operating ju
14、nction temperature will reduce lifetime. PIN FUNCTIONS NAME NO. PIN FUNCTION PVIN1 1 Input supply voltage of half-bridge FETs Q1 and Q2. Connected to the drain of high side FET Q1. a local bypass capacitor from PVIN1 pin to PGND pin should be added. Path from PVIN1 pin to high frequency bypass capac
15、itor and PGND must be as short as possible. PGND 2 PGND is the common power ground of full bridge, connected to the source terminal of low side FETs Q2 and Q4 internally. PVIN2 3 Input supply voltage of half-bridge FETs Q3 and Q4. Connected to the drain of high side FET Q1. Local bypass capacitor fr
16、om PVIN1 pin to PGND pin should be added. Path from PVIN1 pin to high frequency bypass capacitor and PGND must be as short as possible. VIN 4 Input supply voltage of buck convertor. A local bypass capacitor from VIN pin to GND pin should be added. Path from VIN pin to high frequency bypass capacitor
17、 and GND must be as short as possible. GND 5 Power ground of buck convertor. SW3 6 Regulator switching output. Connect SW3 to an external power inductor. BST3 7 Power supply bias for the high-side power MOSFET gate driver of buck convertor. Connect a 0.1uF capacitor from BST3 pin to SW3 pin. SCT6324
18、0 For more information 2018Silicon Content Technology Co., Ltd. All Rights Reserved VDD 8 Buck convertor 5V output voltage, connect 22uF capacitor from this pin to GND. VDD is also the power supply for gate driver of power stage and as the input power for 3.3V LDO. V3P3 9 3.3V LDO output. Connect 1u
19、F capacitor to ground. BST2 10 Power supply bias for the high-side power MOSFET gate driver of Q3 as shown in the block diagram. Connect a 0.1uF capacitor from BST2 pin to SW2 pin. SW2 11 Switching node of the half-bridge FETs Q3 and Q4, as shown in the block diagram. SW1 12 Switching node of the ha
20、lf-bridge FETs Q1 and Q2, as shown in the block diagram. BST1 13 Power supply bias for the high-side power MOSFET gate driver of Q1 as shown in the block diagram. Connect a 0.1uF capacitor from BST1 pin to SW1 pin. VREF 14 Output of the 2.5V LDO. connect 1uF capacitor to ground. ISNS 15 Current dete
21、ction output. The voltage of the pin is proportional to the input current. AGND 16 Analog ground of the IC PWM2 17 PWM logic input to the FET Q3 and Q4 as shown in the Block Diagram. Logic HIGH turns off the low-side FET Q4, and turns on the high-side FET Q3. Logic LOW turns off the high-side FET Q3
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