Basicflow中最终版.ppt

单击此处编辑母版标题样式,单击此处编辑母版文本样式,第二级,第三级,第四级,第五级,11 十一月 2026,Basicflow中最终版,课程目标,学完这个单元后，你应该能够掌握,：,创建一个Milkyway库来容纳你的设计,在启动IC Compiler时会读入所有必要的文件,学会解决常见的错误和警告,时序分析和优化的设置,能在IC Compiler进行布局、时钟树综合和布线的基本流程,Unit Roadmap,数据建立,读入门级网表和时序约束,设置时序库,建立Milkyway库,进行平面规划,基本流程：,布局,时钟树综合,布线,分析,建立时序和RC模型,时序变量,RC和TLU+模式,延迟计算,General IC Compiler Flow,Synthesis,Unit 1,Unit 3,Unit 4,Unit 5,Unit 6,Unit 2,Design Setup,Design Planning,place_opt,clock_opt,route_opt,Chip Finishing,IC Compiler,布局,CTS,布线及优化,IP,ICCompiler,门级网表,平面规划,布局、时钟树综合、布线及优化,工艺文件,TLU+模型,IO放置文件(tdf),综合后网表,时序约束文件SDC,IO pads 放置,Chip/core 边界,Cell rows,wire tracks 建立,宏单元放置,输出,place_opt,clock_opt,route_opt,Chip finishing and DFM,Power plan,标准单元放置,创建时钟树,完成时钟和信号线布线,输出,Floorplan,IC Compiler 数据流程,DEF,MW,Design Planning,Unit Flow:From Setup to Output,Logical Data Setup,Physical Data Setup,place_opt,clock_opt,route_opt,Analysis,Output,逻辑数据,Gate-Level Netlist(s),Logical Libraries.db,link,check_timing,create_clock period 10.set_input_delay max 1.2.set_output_delay max 2.5.set_driving_cell.,Logical(Timing)Constraints,Logical Data Physical Data,place_opt clock_opt route_opt,Analysis Output,Logical Data,读入综合后的门级网表,IC Compiler能够打开Design Compiler生成的Milkyway数据,或是Design Compiler支持的其它格式,可以读入一个或多个文件,read_ddc,read_verilog,read_vhdl,read_verilog file1.v file2.v,Milkyway and DDC can also contain design attributes,!,MY_TOP_DESIGN,不允许相同的例化名,IC Compiler不支持非唯一的设计，例如，一个设计的多个例化具有相同名字！,当读入一个非唯一例化的设计，你的ICC脚本的第一个命令应该是:,current_design MY_TOP_DESIGN,uniquify,PARSER,PARSER1,PARSER2,PARSER3,逻辑库（.db),为所有标准单元(and,or,flipflop,)提供时序和功能信息,为硬件宏单元(IP,ROM,RAM,)提供时序信息,定义驱动/负载设计规则：,最大扇出和跳变,最大/最小电容,进行如下指定：,Logical Libraries.db,set link_library*gates.db io.db rams.db,“*”=Search all designs in memory,要确定所用到的单元包含正确的db,!,CCS Library Support,IC Compiler支持NLDM和CCS(Composite Current Source)库,基于CCS模型具有更加准确的时序、噪声，功耗模型,更精确的连线阻抗,密勒效应,动态的IR压降,多电压阀,温度逆增,NLDM模型对于90纳米及以下是不够精确的，在90纳米及以下要用CCS,模型,CCS Supported Throughout Galaxy,Tools,Timing,Noise,Power,NanoChar,PrimeTime,IC Compiler,Design Compiler,n/a,CCS Support,Milkyway,Signoff,Design,Compiler,IC,Compiler,Galaxy,IC Compiler 如何查找文件?,默认情况下，你必须定义所有文件的路径（不管是相对还是绝对）,你可以指定到哪些路径下寻找文件：,以上路径供IC Compiler用来读入或者找到文件,lappend search_path./design_data./scripts,lappend search_path glob$MW_libs/*/LM,目标库,与link_library 和search_path变量一样，你需要定义用于映射和逻辑优化的逻辑库：,默许情况，target_library只指向标准单元库,set target_library gates.db,*,逻辑参考库,门级网表包含标准单元和宏单元的例化，标准单元和宏单元的时序信息被存放在逻辑参考库里,Link命令将确保把所有例化单元的逻辑参考库都能找到,link,risc_core,nand nor inv ff,sdram_if,Gate-Level Netlist(s),mem.db,gates.db,ip.db,pci_core,link_library,Shortcuts,import_designs orca.v,-format verilog ,-top ORCA_TOP,Replaces:,read_verilog netlist orca.v,current_design ORCA_TOP,uniquify,link,save_mw_cel as ORCA_TOP,Format can be verilog,db,ddc,时序约束,“时序约束”是用来把对设计的时序要求传达给IC Compiler,应与逻辑综合用的是同一个时序约束文件（SDC）,create_clock period 10 get_ports clkset_input_delay 4 clock clk get_ports sd_DQ*set_output_delay 5 clock clkget_ports sd_LDset_load 0.2 get_ports pdevsel_nset_driving_cell lib_cell buf5 get_ports pdevsel_n.,read_sdc timing_constraints.sdc,SDC=Synopsys Design Constraints,约束管理,remove_sdc,Removes all SDC constraints,remove_ideal_network-all,Removes ideal_network attributes,latencies and transitions,remove_annotations,Removes all annotated delays,transition,resistance,capacitance,checks,To remove all settings:,reset_design,Removes all optimization attributes(dont_touch,size_only)and all constraints.,时序检查,在PR之前，必须确保设计是被完全约束的,对于没有被时序约束的路径，IC Compiler将不会对其进行优化,对于缺少外部负载和驱动特性的约束，不进行检查！,check_timing,!,check_timing报告所有没被约束的路径,错误的路径同样被认为是没有被约束的,下面命令是用来验证没有被约束的路径是不是OK,报告设计中设置的错误路径,将这些路径和check_timing报告的路径做比较,report_timing_requirements,check_timing,:False Paths,Physical Data,check_physical_constraints,Constrained andlinked design,PhysicalReference Libraries(Milkyway),Floorplan,IP,Logical Data Physical Data,place_opt clock_opt route_opt,Analysis Output,Physical Data,Physical Libraries,包含标准单元和宏模块布局所必需的物理信息,定义布局的unit tile单元拼接,reference point(typically 0,0),Dimension,“bounding box”,Pins(direction,layer and shape),VDD,GND,A,B,Y,NAND_1,Blockage,Symmetry,(X,Y,or 90),F,Abstract View,FF,BUF,INV,NOR,unit tile(site),Reference Libraries(Milkyway),Milkyway 参考库,标准单元信息储存在“视图”，例如：,CEL:完整的版图视图,FRAM:用于布局布线的抽象视图,LM:带时序和功耗信息的逻辑模型,(optional*),CEL/,FRAM/,and2a1,and2a2,.,xor3a27,and2a1,and2a2,.,xor3a27,VENDOR_XYZ_std_cell_90nm,Used for P&R,lib_max.db,lib_min.db,.,LM/,工艺文件(.tf file),工艺文件对每一种工艺都是唯一的,包含金属层的技术参数:,每个金属层/过孔的层号和命名,介电常数,每个金属层/过孔的物理和电气特性,每个金属层/过孔的设计规则（最小线宽和最小线间距度等）,各种电量的单位和精度,要显示层的颜色和模式,Example of a Technology File,Technology ,dielectric=3.7,unitTimeName=ns,timePrecision=1000,unitLengthName=micron,lengthPrecision=1000,gridResolution=5,unitVoltageName=v,.,Layer m1,layerNumber=16,maskName=metal1,pitch=0.56,defaultWidth=0.23,minWidth=0.23,minSpacing=0.23,.,abc_6m.tf,指定参考库,通过创建一个设计库,！,怎样指定物理参考库和技术文件呢？,create_mw_lib,design_lib_orca,-technology,techfile.tf,-mw_reference_library,“sc io ram32”,-open,Now you are ready to apply the floorplan,Applying the Floorplan,RAM,Site Arrays,Array of placement sites,Cluster,Hard Boundary,Keepouts&PG nets,Port Locations,Signal I/O,Fixed Cells,Example:RAM placement,read_def my_floorplan.def allow_physical,Allows physical-only objects like PG nets.,Copying the Floorplan from another MW Cell,如果一个设计已经在IC Compiler or JupiterXT平面规划过，再读入相同设计的新网表，这一步是很有用的,Cell_A,Cell_B,copy_floorplan,Existing un-floorplanned cell,Opening a MW Design from JupiterXT,lappend search_path./db,set link_library*gates.db rams.db,set target_library gates.db,open_mw_lib my_jxt_lib.mw,open_mw_cel floorplanned,set_tlu_plus_files.,;explained later,remove_sdc,read_sdc mydesign.sdc,place_opt,clock_opt,route_opt,save_mw_cel-as routed,Apply your timing constraints for P&R,.,检查物理约束,检查库和平面规划:,物理库,逻辑库不一致,Core中放置单元的面积够不够,狭窄布局区域的警告,报告物理单元的数目、已用的sites和总利用率,RC参数,可以通过man page查看更多细节,check_physical_constraints,建立设计这一步做完，要保存Milkyway设计单元,默认情况下，,link_library,search_path,target_library and TLU+settings,都会保存在CEL里,如果库文件要移到其他地方，必须要重新设置,当你重新打开CEL，默认情况下储存的设置是不会被用除非这样设置:,set auto_restore_mw_cel_lib_setup true,open_mw_cel orca_init,save_mw_cel as orca_init,保存和导入设计单元,设计库,Design Library,design_lib_orca,Technology File,abc_6m.tf,MWStandard cells,MWMacro cells,MW,Padcells,sc.db,io.db,orca_init,orca.v,orca.sdc,orca.def,Container for all data!,link_librarytarget_library,settings,TLU+RC models,more later,UNIX Structure of a Design Milkyway Database,./design_lib_orca/,CEL/,Database T.O.C,technology data etc.,.,orca_init:1,Saved Cell,MW Design Library,lib,lib_1,lib_bck,UNIX Manipulation of a Milkyway Database,UNIX%cd CEL,UNIX%rm ORCA_placed,UNIX%cp Joes_Lib/ORCA_placed .,STOP,./design_lib_orca/,CEL/,ORCA_init,ORCA_floorplanned,ORCA_placed,ORCA_cts,ORCA_routed,lib,lib_1,lib_bck,T.O.C.Corrupted!,Test for Understanding,List the 2 variables that need to be set up to successfully read all design files!,What is the difference between the,link_library,and the,target_library,?,IC Compiler requires a chip-level floorplan including IO PADs.,True/False,A floorplan must always be input to IC Compiler by reading a DEF file.,True/False,Which of the following is,not,recommended?,lappend search_path my_path,set search_path my_path,set search_path$search_path my_path,2 Minutes!,Summary,Gate-Level Netlist,Logical Library.db,Logical Constraints.sdc,read_sdc,read_def,check_timingcheck_physical_constraints,read_verilog/vhdl/ddc,set link_library*sc.dbset target_library sc.db,create_mw_lib technology,mw_reference_library,IC,Compiler,Physical ConstraintsDEF or MW library,Ready for Place&Route,MW Reference,Libraries,+tech file,Or:import_design,IC Compiler Recommended Setup,#,load common settings&useful procedures,source./ref/icc_settings.tcl,lappend search_path./scripts./ref/sdb./ref/db,set symbol_library sc_icon.sdb io_icon.sdb,set link_library*sc_max.db io.db ram16x128_max.db,set target_library sc_max.db,create_mw_lib design_lib_orca -open-technology techfile.tf -mw_reference_library mw/sc mw/io mw/ram32,set mw_logic0_net VSS,set mw_logic1_net VDD,import_designs design.ddc,-format ddc ,-top ORCA_TOP,read_def allow_physical design.def,save_mw_cel overwrite,#,CEL saved as ORCA_TOP,All setup done first and stored in,.synopsys_dc.setup,.synopsys_dc.setup,.synopsys_dc.setup,.synopsys_dc.setup,$SYNOPSYS/admin/setup,user,ICC startup directory,Users Specific,Project Setup,Users General,Setup,Standard,Setup,IC Compiler 3个初始化文件,在.synopsys_dc.setup命令在工具打开时自动导入，导入顺序为1、2、3，且3有最高的优先级,2,1,3,布局阶段,在布局&优化之前:,不要对设计单元过约束,约束要符合设计规范,布局前先报告时序情况,采用忽略互联线影响来查找不合实际和不正确的约束,set_zero_interconnect_delay_mode true,Warning:Timer is in zero interconnect delay mode.(TIM-177),report_constraint all,report_timing,set_zero_interconnect_delay_mode false,Information:Timer is not in zero interconnect delay mode.(TIM-176),Logical Data Physical Data,place_opt clock_opt route_opt,Analysis Output,place_opt,布局和优化,place_opt,反复执行布局和优化.,DTDP:布局的首要目标是建立时间,slack为正,Logic moved closer together for shorter nets,Cells upsized for optimal drive/speed,时钟树综合,设置时钟树综合时选项/例外,运行,clock_opt,命令,创建时钟树,执行增量的逻辑和布局优化,运行时钟树优化,对时钟网络进行布线,通过设置，clock_opt,还能进行,修复hold time违规,执行内部时钟平衡,Logical Data Physical Data,place_opt clock_opt route_opt,Analysis Output,clock_opt,clock_opt,Routing,布线器进行:,Global Route,Track Assignment,Detailed Route,然后执行大量的逻辑、布局、布线和串扰优化来产生最好的布线结果,Logical Data Physical Data,place_opt clock_opt route_opt,Analysis Output,route_opt,route_opt,分析,检查执行place_opt 和 route_opt命令后屏幕输出的设计总结:,利用率,WNS Worst Negative Slack,TNS Total Negative Slack,单元放置的合法,单元数量和面积,设计规则违规,用report_qor命令:,每个路径组(clock group)WNS/TNS,其它统计信息,Logical Data Physical Data,place_opt clock_opt route_opt,Analysis Output,Analysis,Analysis Details,产生更加详细的报告,显示所有违规路径终点,report_constraint all_violators,详细显示建立时间最坏的那条路径,report_timing,报告物理设计统计信息(如.利用率),report_design-physical,分析阻塞,阻塞图(GUI),report_congestion,采用一致性的名字,Imperative when exporting data,always!,在 Milkyway数据库中保存设计单元,保存 Verilog网表,仅保存平面规划信息,change_names hierarchy rules verilog,save_mw_cel-as routed,write_def-output floorplan.def,write_floorplan floorplan.tcl,write-format verilog-hierarchy-output routed.v,Output,Logical Data Physical Data,place_opt clock_opt route_opt,Analysis Output,Output,Example“run”Script,lappend search_path./design_data./db./tlup,set link_library*gates.db rams.db,set target_library gates.db,create_mw_lib my_lib.mw,technology tech_file.tf,mw_reference_library mwlib/gates mw_lib/rams“,-open,import_designs my_design.v,-format verilog ,-top MYDESIGN,set_tlu_plus_files,-max_tluplus abc_max.tlup,-min_tluplus abc_min.tlup,-tech2itf_map abc.map,;explained later,read_sdc my_design.sdc,check_timing,read_def-allow_physical my_design.def,check_physical_constraints,place_opt,clock_opt,route_opt,save_mw_cel-as routed,UNIX$icc_shell f run.tcl|tee myrun.log,run.tcl,Local Disk Space Usage,在IC Compiler进行版图设计流程时,要求足够的磁盘空间去存储数据，例如:,上面表显示通过每个步骤要求的磁盘空间增加，因此完成150K门的设计,需要 56+62+120=238 MB.,Design size Milkyway database*size,(instances)place_opt clock_opt route_opt,-,150K 56MB 62MB 120MB,250K 150MB 178MB 303MB,400K 242MB 269MB 460MB,625K 277MB 325MB 569MB,700K 344MB 419MB 741MB,850K 917MB 950MB 1.5GB,*this includes all CEL/ROUTE/PARA/.views plus any CEL attachments,静态时序分析,IC Compiler的静态时序分析设置与 Design Compiler、PrimeTime相同,用IC Compiler进入分析前,需要对库和操作条件设置.如:,set link_library*abcmax.db,set_operating_conditions,analysis_type on_chip_variation,-max abc_wc-max_library abc_max,Using operating conditions abc_wc found in library abc_max.,report_timing delay max|min,More Complex Setup in Unit 4!,时序优化设置,在IC Compiler中，由许多变量和命令来控制时序优化.例如：,set enable_recovery_removal_arcs true,set timing_self_loops_no_skew true,set_cost_priority max_delay max_capacitance,set_ahfs_options-enable_port_punching true,记住所有这些变量和命令是很麻烦 用GUI 提供帮助!,用 GUI 执行时序优化设置,然后把这些变量和命令拷到设置文件中,时序优化设置,(2/2),基于单元和网络计算时序延时,ICC为每个单元和网络计算延时,为计算延时，ICC需要知道每个网络的寄生RC,Cell Delay=,(Input Transition Time,C,net,+C,pin,),Net Delay=,(R,net,C,net,+C,pin,),0.5 ns,Cnet,Cpin,Rnet,TLU+模型,IC Compiler用网络的几何形状和TLU+查找表来计算 C,and,R,超深亚微米加工的效应模型,Single,Process File(ITF),TLU+,ICC,PC,Astro,nxtgrd,Star-RCXT,超深亚微米加工效应,Conformal Dielectric,Metal Fill,Shallow Trench Isolation,Copper Dishing:,Density Analysis,Width/Spacing,Trapezoid Conductor,See Appendix B for details,Generating TLU+Models,ITF(加工文件)由Foundry厂提供,TLU+模型通常是不提供,从ITF产生TLU+,Where:,-itf2TLUPlus,generates TLU+instead of nxtgrd file,-i,is the ITF file,-o,is the output,binary TLU+model file,unix%grdgenxo-itf2TLUPlus-i,-o,Always use the latest Star-RCXT release to generate the models.,set_tlu_plus_files,-max_tluplus abc_max.tlup,-min_tluplus abc_min.tlup,-tech2itf_map abc.map,Loading TLU+Models,IC Compiler 检查search_path 去查找 TLU+files,对TLU+设置执行一致性检查,确保正确的TLU+和map文件,check_tlu_plus_files,映射文件,映射文件从.tf(MW技术文件)层/过孔名映射到Star-RCXT，.itf层/过孔名。,Layer METAL,layerNumber=14,maskName=,metal1,DIELECTRIC cm_extra3 THICKNESS=0.06 ER=4.2,CONDUCTOR,cm,THICKNESS=0.26 WMIN=0.16,DIELECTRIC diel1d THICKNESS=0.435 ER=4.2,abc.itf,abc.tf,conducting_layers polypoly,metal1cm,metal2cm2,abc.map,计算单元和网络延时,从 TLU+模型中可知道网络的寄生RC，则可计算延时,对于单元延时，只需要C,total,/C,eff,计算算法计算网络延时有：,Elmore,Arnoldi,C1,R1,R2,R3,C3,C4,U2,U1,C2,预布线时的延时计算算法,布局后布线前，基于虚拟布线来估计线长度,由于虚拟布线只是一种估算，用,Elmore,模型进行延时计算,Pin-to-pin timing,Virtual Route,布线后的延时计算算法,布线后，具体线网已经明确，因此抽取更加精确,默认情况下仍用Elmore 模型,在后布线计算时可打开Arnoldi,模型,Detailed Route,Basic Flow Summary,You should now be able to:,Create a Milkyway library to hold your design,Read all necessary files required to run IC Compiler,resolving common errors/warnings,Set up timing for analysis and optimizations,Execute the basic flow for placement,CTS and routing in IC Compiler,45 minutes,Lab 1:Baseline flow for IC Compiler,Goals:,Setup design database and timing,Perform baseline place,cts&route operations with associated default optimizations,Create MW database with attached libraries,place_opt,clock_opt,route_opt,Analysis and Output,Read design,constraints,floorplan,设置设计资料库课时间,在默认的优化下执行基本操作流程：布局、时钟树综合和布线操作。,Appendix A,MW参考库的准备,Migration from DB/PDB to MW:Terminology,DC/PC Terminology,Milkyway Terminology,Library Compiler(compile library),read_lib,write_lib,Milkyway tool(create/editMilkyway Library),read_lef,read_plib,Database(db),Library db,(timing),PDB,(physical),Design db/ddc,Milkyway Library,Library db,(can be part of Ref Lib as LM view),Reference LibraryDesign Library,Setup without using Milkyway:,search_pathlink_librarytarget_library,Setup using Milkyway library:,search_pathlink_librarytarget_library set_mw_lib_reference,Reference Library Requirements,逻辑库(.db),物理库（(MW),专用集成电路厂家提供的库,Physical Library,Cell size,-,bufbd1 (1.6400,3.6900),sdbfb1 (14.7600,3.6900),filler (13.1200,3.6900),Logical Library,Cell Attribute,-,bufbd1,sdbfb1 t(mux_ff),set target_library art005.db,set_mw_lib_reference art005,libraries must match,cell names,pins,physical only cell,test cell,icc_shell,check_physical_constraints,.,Physical Library:design_lib_orca,Routing layer:METAL width:160 pitch:410 space:180,Routing Layer:METAL Resistance:6.4e-05 Capacitance:4.19e-05,Routing layer:METAL2 width:200 pitch:410 space:210,Routing Layer:METAL2 Resistance:3.7e-05 Capacitance:2.23e-05,Routing layer:METAL3 width:200 pitch:515 space:2