DDR-SDRAM-fundamental(ppt文档).ppt

FIC 1First International Computer R&D H/W Training DDR SDRAM Fundamental FIC 2Section Agenda-DDR SDRAM Fundamentalsn nEvolution towards the DDR SDRAMn nSignal Descriptionn nDevice Operationn nPower-Up and Initializationn nAC/DC Spec.n nDDR SDRAM ModuleFIC 3DDR SDRAM-Evolution towards the DDR SDRAM1.The address and command inputs to be sampled on the rising edge of the input clock(no change from SDRAM)2.The data to be input or output is sampled or driven relative to BOTH edges of the clock 3.A bi-direction data strobe(选通脉冲选通脉冲)pin is introduced(same direction as data)4.A DLL(or similar circuit)is to be used to shift the output DQ and DQS align with the input clock5.DQM pin has been changed to a DM for DDR6.The mode register has been expanded and eliminate a few unused SDR SDRAM mode7.A novel way of using CKE has been developed(Outputs in Hi-Z)8.An optional QFC pin allows DIMMs with FET isolated from bus9.66 pin,400mil TSOP II package in x4,x8,x16FIC 4DDR SDRAM-Signal DescriptionFIC 5DDR SDRAM-Signal DescriptionBasic DDR SDRAM READ cycleFIC 6DDR SDRAM-Signal DescriptionBasic DDR SDRAM WRITE cycleFIC 7DDR SDRAM-Signal DescriptionCK and CK(Clock)CK and CK#are differential clock inputs.All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#.Output data(DQs and DQS)is referenced to the crossings of CK and CK#.CKE(Clock Enable)CKE activates and deactivates the internal clock,input buffers and output drivers.CKE must be maintained HIGH throughout read and write accesses.CKE LOW PRECHARGE POWER-DOWN and ACTIVE POWER-DOWN(row ACTIVE in any bank).Input buffers(excluding CK,CK#and CKE)are disabled SELF REFRESH operations(all banks idle),Input buffers(excluding CKE)are disabled FIC 8DDR SDRAM-Signal DescriptionCS#(Chip Select)1.CS#enables and disables the command decoder.All commands are masked when CS#is registered HIGH.2.CS#provides for external bank selection on systems with multiple banks.3.CS#is considered part of the command code.RAS#,CAS#,WE#(Command)RAS#,CAS#and WE#(along with CS#)define the command being entered.LDM,UDM(Data Mask)1.DM is an input mask signal for write data.2.Write data is masked when DM is sampled HIGH along with thatinput data during a WRITE access.3.DM is sampled on both edges of DQS.4.One DM for x4,x8,two DMs for x16FIC 9DDR SDRAM-Signal DescriptionBA0,BA1(Bank Address)1.BA0 and BA1 define to which bank an ACTIVE,READ,WRITE or PRECHARGE command is being applied.2.BA0 and BA1 define which mode register(mode register or extended mode register)is loaded during the LOAD MODE REGISTER command.A0-A11(Address Inputs)1.Provide the row address for ACTIVE commands,and 2.The column address and auto pre-charge bit(A10)for Read/Write commands.3.A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank(A10 LOW,bank selected by BA0,BA1)or all banks(A10 HIGH).4.The address inputs also provide the op-code during a MODE REGISTER SET command.DQ0-7(Data Input/Output)Data bus for x8FIC 10DDR SDRAM-Signal DescriptionLDQS,UDQS,I/O(Data Strobe)1.Output with read data,input with write data.2.DQS is edge-aligned with read data,centered in write data.3.It is used to capture data.4.One DQS for x4,x8,two DQSs for x16QFC#,Output,OD,(FET Control)x4 only,used to control isolation switches on modules.Open drain output.DNU on x8 or x16 option.VDDQ,VSSQ(DQ Power Supply)+2.5V,0.2V.Isolated on the die for improved noise immunity.VDD,VSS(Power Supply)+2.5V,0.2V.VREFSSTL_2 reference voltage.+1.25VFIC 11SDRAM-Signal Description-QFC#Theory on QFC#If there are several DRAMs sharing a data line on a DIMM,or the stub length to the DIMM is long,then a pass-gate FET switch which replace the stub termination resister of an SSTL net can reduce the line capacitance and allow faster data signaling.It is expected that.the ON impedance of this pass-gate switch is 20 OhmsInput capacitance of the switch be less then 4pfSwitching time to be less than 1ns The pass-gate switch is envisioned as a stand-alone device controlling data I/O and located physically very close to the cardedge of a DIMMFIC 12DDR SDRAM-Power-Up and Initialization SequencePOWER UP and Initialization.1.Apply power and attempt to maintain CKE at a low state-Apply VDD before or at the same time as VDDQ.Apply VDDQ before or at the same time as VTT&Vref.2.Start clock and maintain stable for a minimum of 200us.3.Apply NOP&take CKE high.4.Issue pre-charge commands for all banks of the device.5.Issue EMRS to enable DLL.Low to BA1 High to BA0 and Low”to A0-A1,and the rest address pins,A2A11)FIC 13DDR SDRAM-Power-Up and Initialization Sequence6.Issue a MRS for DLL reset.High to A8 and Low to BA0 Wait 200 cycles to lock the DLL.7.Issue pre-charge commands for all banks of the device.8.Issue 2 or more auto-refresh commands.9.Issue a mode register set command with low to A8 to initialize device operation.FIC 14DDR SDRAM-Device OperationFIC 15DDR SDRAM-Device OperationFIC 16DDR SDRAM-Device OperationFIC 17DDR SDRAM-Device OperationFIC 18DDR SDRAM-Device OperationROW Active 1.The Bank Activation command is issued by holding CS#and RAS#low,CAS#and WE#high with at the rising edge of the clock(CK),where BA0BA1 are indicated the bank to be activated,MA011 are Row address.2.The Bank Activation command must be applied before any Read or Write operation is executed.3.tRCD,the delay from the Bank Activation command to the first read or write command must meet or exceed.4.Once a bank has been activated,it is opened and it must be pre-charged before another Bank Activation command can be applied to the same bank.5.tRRD,the minimum time interval between interleaved Bank Activation commands(Bank A to Bank B).FIC 19DDR SDRAM-Device Operationn nROW ActiveFIC 20DDR SDRAM-Device OperationBurst Read 1.The command is issued by holding CS#and CAS#low,RAS#and WE#high with at the rising edge of the clock(CK),BA0,BA1 inputs selects the bank,and MA0MAj column address,A10 determines whether or not auto pre-charge is used.2.If auto pre-charge is selected,the row being accessed will be pre-charged at the end of the READ burst.3.The first output data is available after the CAS Latency from the READ command,FIC 21DDR SDRAM-Device OperationBurst Write 1.The command is issued by holding CS#,CAS#and WE#low and RAS#high with at the rising edge of the clock(CK),(BA0BA1the bank,MA0MAj column address,MA10 pre-charge or not.)2.If auto pre-charge is selected,the row being accessed will be pre-charged at the end of the Write burst.3.The first data of a burst write cycle must be applied on the DQ pins tDS prior to data strobe DQS edge 4.The first data strobe edge and DATA are enabled after tDQSS from the rising edge of the clock(CK)that the write command is issued.tDS:Data-in setup time tDQSS:Write command to first DQS FIC 22DDR SDRAM-Device OperationBurst Stop1.The burst stop command is initiated by having RAS and CAS high with CS and WE low at the rising edge of the clock(CK).2.The burst stop command is used to terminate a burst read operation before it has been completed,however,is not supported during a write burst operation.3.When issued during a burst read cycle,the data and DQS (Data Strobe)go to a high impedance state after a delay of (LBST)”CAS latency”set in the mode register.4.BST is an undefined command during Read with auto prec-harge and shall not be used.FIC 23DDR SDRAM-Device OperationDM masking1.The DDR SDRAM has a data mask function that can be used in conjunction with data write cycle,not read cycle.2.When the data mask is activated(DM high)during write operation,DDR SDRAM does not accept the corresponding data.3.DM to data-mask latency is zero4.DM must be issued at the rising or falling edge of data strobe.FIC 24DDR SDRAM-Device OperationPRECHARGE 1.The pre-charge operation is performed on an active bank by asserting low on CS,RAS,WE and A10/AP with valid BA0 BA1 of the bank to be pre-charged.2.Asserted anytime after tRAS(min)3.tRP is defined as the minimum number of clock cycles required to complete4.Make sure that burst write is completed tWR(min.)must be satisfied or DM is used to inhibit writing5.The maximum time any bank can be active is specified by tRAS(max).6.At the end of pre-charge,the bank enters the idle state FIC 25DDR SDRAM-Device OperationDDR SDRAM Termination functionalityRead Interrupted by a Read(Read+Read)Read Interrupted by a Write&Burst Stop (Read+BST+Write)Read Interrupted by a Precharge(Read+Pre-charge)Write Interrupted by a Write(Write+Write)Write Interrupted by a Read DM(Write+Read)Write Interrupted by a Precharge DM(Write+Precharge)FIC 26DDR SDRAM-Device OperationRead With Auto Pre-charge1.If a read with auto pre-charge command is initiated,the DDR SDRAM automatically enters the pre-charge operation BL/2 clock later from a read with auto pre-charge command when tRAS(min)is satisfied.2.Or the start point of pre-charge operation will be delayed until tRAS(min)is satisfied.3.Once the pre-charge operation has started the bank cannot be reactivated and the new command can not be asserted until the pre-charge time(tRP)has been satisfied.FIC 27DDR SDRAM-Device OperationWrite with Auto Precharge1.If A10 is high when write command is issued,the write with auto pre-charge function is performed.2.Any new command to the same bank should not be issued until the internal pre-charge is completed.3.The internal pre-charge begins after keeping tWR(min).FIC 28DDR SDRAM-Device OperationRead Interrupted by a Read1.A Burst Read can be interrupted before completion of the burst by new Read command of any bank.2.When the previous burst is interrupted,the remaining addresses are overridden by the new address with the full burst length.3.The data from the first Read command continues to appear on the outputs until the CAS latency from the interrupting Read command is satisfied.4.Read to Read interval is minimum 1 Clock.FIC 29DDR SDRAM-Device OperationRead Interrupted by a Write&Burst Stop1.For Write commands interrupting a Read burst,a Burst Terminate command is required to stop the read burst and tri-state the DQ bus prior to valid input write data.2.Once the Burst Terminate command has been issued,the minimum delay to a Write command=RU(CL)CL is the CAS Latency and RU means round up to the nearest integer.3.It is illegal for a Write command to interrupt a Read with auto pre-charge command.FIC 30DDR SDRAM-Device OperationRead Interrupted by a Pre-charge1.A Burst Read operation can be interrupted by pre-charge of the same bank.2.A pre-charge command to output disable latency is equivalent to the CAS latency.3.For the earliest possible Pre-charge command without interrupting a Read burst,the Pre-charge command may be given on the rising clock edge which is CL clock cycles before the end of the Read burst.4.A new Bank Activate command may be issued to the same bank after tRP.(tRP is an analog delay that needs to be converted into clock cycles.)FIC 31DDR SDRAM-Device OperationWrite Interrupted by a Write1.A Burst Write can be interrupted before completion of the burst by a new Write command.2.When the previous burst is interrupted,the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied.FIC 32DDR SDRAM-Device OperationWrite Interrupted by a Read&DM1.A burst write can be interrupted by a read command of any bank.2.The DQs must be in the high impedance state at least one clock cycle before the interrupting read data appear on the outputs to avoid data contention.3.Any residual data from the burst write cycle must be masked by DM.4.The delay from the last data to read command(tCDLR=tWTR)is required to avoid the data contention.5.Read command in-terrupting write can not be issued at the next clock edge of that of write command.(minimum Write to Read command delay is 2 clock)FIC 33DDR SDRAM-Device OperationWrite Interrupted by a Read&DM1.A burst write operation can be interrupted before completion of the burst by a pre-charge of the same bank.2.Random column access is allowed.A write recovery time(tWR)is required from the last data to pre-charge command.3.When pre-charge command is asserted,any residual data from the burst write cycle must be masked by DM.(DQS is still required)FIC 34SDRAM-Device OperationSELF REFRESH1.A self refresh command is defined by having CS,RAS,CAS and CKE held low with WE high at the rising edge of the clock(CK).2.Once the self refresh command is initiated,CKE must be held low to keep the device in self refresh mode.3.During the self refresh operation,all inputs except CKE are ignored.The clock is internally disabled during self refresh operation to reduce power consumption.4.The self refresh is exited by supplying stable clock input before returning CKE high,asserting deselect or NOP command and then asserting CKE high for longer than tXSR for locking of DLL.FIC 35SDRAM-DC/AC SpecificationFIC 36SDRAM-DC/AC SpecificationTiming reference 1.The input rise and fall slew rate shall be 1V/ns with a 20 tolerance where are measured from 20%to 80%points of nominal input voltage swings.2.The timing reference point for the differential clock is when the CK and CK#signals cross during a transition3.When reference is made to rising or falling clock edges,this reference is made to CK pin4.For the single data rate inputs,the timing reference point is VREF5.For WRITE,the double data rate input signals(DQS,DM&Input data)the timing reference point is VREF6.For READ the double data rate ouput signals(DQS&Output data)the timing reference point is VTTFIC 37SDRAM-DC/AC SpecificationSpecificationAC CHARACTERISTICS-7-75-8PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX UNITS CK high-level width t CH 0.45 0.55 0.45 0.55 0.45 0.55 t CK CK low-level width t CL 0.45 0.55 0.45 0.55 0.45 0.55 t CKFIC 38SDRAM-DC/AC SpecificationFIC 39SDRAM-DC/AC SpecificationFIC 40SDRAM-DC/AC SpecificationFIC 41SDRAM-DDR SDRAM ModuleFIC 42The End