单片机-外文翻译-英文文献-中英版-at89s51概述.doc

The Description of AT89S51
1 General Description
The AT89S51 is a low-power, high-performance CMOS 8-bit microcontroller with 4K bytes of In-System Programmable Flash memory. The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard 80C51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with In-System Programmable Flash on a monolithic chip, the Atmel AT89S51 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications.
The AT89S51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, two 16-bit timer/counters, a five-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes.
The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next external interrupt or hardware reset.
2 Ports
Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pull-ups are required during program verification.
Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups.
Port 1 also receives the low-order address bytes during Flash programming and verification.
Port Pin
Alternate Functions
P1.5
MOSI (used for In-System Programming)
P1.6
MOSO (used for In-System Programming)
P1.7
SCK(used for In-System Programming)

Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.
Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull-ups. Port 3 receives some control signals for Flash programming and verification. Port 3 also serves the functions of various special features of the AT89S51, as shown in the following table.
Port Pin
Alternate Functions
P3.0
RXD(serial input port)
P3.1
TXD(serial output port)
P3.2
INT0(external interrupt 0)
P3.3
INT1(external interrupt 1)
P3.4
T0(timer 0 external input)
P3.5
T1(timer 1 external input)
P3.6
WR(external data memory write strobe)
P3.7
RD(external data memory read strobe)

3 Memory Organization
MCS-51 devices have a separate address space for Program and Data Memory. Up to 64K bytes each of external Program and Data Memory can be addressed.
3.1 Program Memory
If the EA pin is connected to GND, all program fetches are directed to external memory. On the AT89S51, if EA is connected to VCC, program fetches to addresses 0000H through FFFH are directed to internal memory and fetches to addresses 1000H through FFFFH are directed to external memory.
3.2 Data Memory
The AT89S51 implements 128 bytes of on-chip RAM. The 128 bytes are accessible via direct and indirect addressing modes. Stack operations are examples of indirect addressing, so the 128 bytes of data RAM are available as stack space.
4Watchdog Timer (One-time Enabled with Reset-out)
The WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets. The WDT consists of a 14-bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, it will increment every machine cycle while the oscillator is running. The WDT timeout period is dependent on the external clock frequency. There is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH pulse at the RST pin.

4.1 Using the WDT
To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, the user needs to service it by writing 01EH and 0E1H to WDTRST to avoid a WDT overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH), and this will reset the device. When the WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at least every 16383 machine cycles. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write-only register. The WDT counter cannot be read or written. When WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET pulse duration is 98xTOSC, where TOSC = 1/FOSC. To make the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset.
4.2 WDT DURING Power-down and Idle
In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-down mode, the user does not need to service the WDT. There are two methods of exiting Power-down mode: by a hardware reset or via a level-activated external interrupt, which is enabled prior to entering Power-down mode. When Power-down is exited with hardware reset, servicing the WDT should occur as it normally does whenever the AT89S51 is reset. Exiting Power-down with an interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for the interrupt used to exit Power-down mode. To ensure that the WDT does not overflow within a few states of exiting Power-down, it is best to reset the WDT just before entering Power-down mode. Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine whether the WDT continues to count if enabled. The WDT keeps counting during IDLE (WDIDLE bit = 0) as the default state. To prevent the WDT from resetting the AT89S51 while in IDLE mode, the user should always set up a timer that will periodically exit IDLE, service the WDT, and reenter IDLE mode.
With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the count upon exit from IDLE.

AT89S51概述
1 一般概述
该AT89S51是一个低功耗，高性能CMOS 8位微控制器,可在4K字节的系统内编程的闪存存储器。该设备是采用Atmel的高密度、非易失性存储器技术和符合工业标准的80C51指令集和引脚。芯片上的Flash程序存储器在系统中可重新编程或常规非易失性内存编程 。通过结合通用8位中央处理器的系统内可编程闪存的单芯片， AT89S51是一个功能强大的微控制器提供了高度灵活的和具有成本效益的解决办法，可在许多嵌入式控制中应用。
在AT89S51提供以下标准功能： 4K字节的Flash闪存 ， 128字节的RAM ， 32个 I / O线，看门狗定时器，两个数据指针，两个16位定时器/计数器， 5向量两级中断结构，全双工串行端口，片上振荡器和时钟电路。此外， AT89S51设计了可降至零频率的静态逻辑操作和支持两种软件可选的节电工作模式。
在空闲模式下停止CPU的工作，但允许RAM 、定时器/计数器、串行接口和中断系统继续运行。掉电模式保存RAM中的内容，停止振荡器工作并禁止其它所有部件工作，直到下一个外部中断或硬件复位。
2 端口
P0端口是一个8位漏极开路双向I / O端口。作为一个输出端口，每个引脚可驱动8个TTL输入。对端口写“1”可作为高阻抗输入端用。在访问外部程序和数据存储器时，P0端口也可以配置为复低阶地址/数据总线。在访问期间激活内部上拉电阻。在Flash编程时，PO端口接收指令字节，而在程序校验时，输出指令字节，同时要求外接上拉电阻。
P1端口是一个带内部上拉电阻的8位双向I /O端口。P1端口的输出缓冲级可以驱动四个TTL输入。对端口写“1”，通过内部的上拉电阻把端口拉到高电平，此时可作为输入口。作为输入口时，因为内部存在上拉电阻，某个引脚被外部信号拉低时会输出一个电流（IIL），Flash编程和程序校验期间，P1接收低8位地址。
端口引脚
第二功能
P1.5
MOSI(用于ISP编程)
P1.6
MISO（用于ISP编程）
P1.7
SCK(用于ISP编程)
P2端口是一个带有内部上拉电阻的8位双向I/O端口。P2端口的输出缓冲级可驱动（吸收或输出电流）4个TTL输入。对端口写“1”，通过内部的上拉电阻把端口拉到高电平，此时可作输入口。当作输入口使用时，因为内部存在上拉电阻，某个引脚被外部信号拉低时会输出一个电流（IIL）。在访问外部程序存储器或16位地址的外部数据存储器（例如执行 MOVX @ DPTR指令 ）时，P2端口送出高8位地址数据。 在访问8位地址的外部数据存储器（例如执行MOVX@Ri指令）时，P2端口上的内容（即特殊功能寄存器（SFR)区中P2寄存器的内容），在整个访问期间不变。Flash编程或校验时，P2也可接收高位地址和其它控制信号。
P3端口是一组带有内部上拉电阻的8位双向I/O端口。P3端口输出缓冲级可驱动（吸收或输出电流）4个TTL逻辑门电路。对P3端口写入“1”时，他们被内部上拉电阻拉高并作为输入端口。当作输入端时，被外部拉低的P2端口将用上拉电阻输出电流（IIL）．Ｐ３端口还接收一些用于Flash闪存编程和程序校验的控制信号。P3端口可以采用AT89S51的
各种特殊功能，如下表所示。
端口引脚
第二功能
P3.0
RXD(串行输入端口)
P3.1
TXD(串行输出端口)
P3.2
INT0(外部中断0)
P3.3
INT1（外部中断1）
P3.4
T0(定时/计数器0外部输入）
P3.5
T1（定时/计数器1外部输入）
P3.6
WR（外部数据存储器写选通）
P3.7
RD（外部数据存储器读选通）
3 存储器结构
MCS-51单片机内核采用程序存储器和数据存储器空间分开的结构，均具有64KB外部程序和数据的寻址空间。
3.1 程序存储器
如果的EA引脚接地（GND），全部程序都可以执行外部存储器。在AT89S51 ，如果EA连接到电源+（VCC） ，程序首先执行地址从0000H到FFFH内部存储器，在执行地址从1000H到FFFFH的外部程序存储器。
3.2 数据存储器
AT89S51具有128字节的内部RAM 。 这128字节都可以通过直接和间接寻址方式访问，堆栈操作可利用间接寻址方式进行，因此， 128字节都可以可作为堆栈空间。

4看门狗定时器 （WDT）
看门狗定时器（WDT）是为了解决CPU程序运行时可能进入混乱或死循环而设置，它由一个14bit计数器和看门狗定时器复位SFR（WDTRST）构成。外部复位时，看门狗定时器（WDT）默认为关闭状态，要打开WDT，用户必须按顺序将01EH和0E1H写到WDTRST寄存器（SFR地址为0A6H），当启动了WDT，它会随警惕振荡器在每个机器周期计数，除了硬件复位或WDT溢出复位外没有其它方法关闭WDT，当WDT溢出，将使RST引脚输出高电平的复位脉冲。
4.1使用看门狗定时器（WDT）
用户在打开WDT时，需要按次序将01EH和0E1H写到WDTRST寄存器(SFR的地址为0A6H)，当WDT打开后，需要在一定的时候将01EH和0E1H写道WDTRST寄存器以避免WDT计数溢出。14位WDT计数器达到16383（3FFFH），WDT将溢出并使用器件复位。WDT打开时，它会随着晶体振荡器在每个机器周期计数，这意味着用户必须在小于每个16383机器周期内复位WDT，也即写01EH和0E1H到WDTRST寄存器，WDTRST为只写寄存器。WDT计数器既不可读也不可写，当WDT溢出时，通常将使RST引脚输出高电平的复位脉冲。复位脉冲持续时间为98xTosc，而Tosc=1/Fosc(晶体振荡频率)。为使WDT工作最优化，必须在合适的程序代码时间段周期地复位WDT防止WDT溢出。
4.2掉电和空闲模式下的WDT
掉电时期，晶体振荡停止，看门狗定时器也停止。掉电模式下，用户不嗯那个在复位看门狗定时器。有两种方法可以推出掉电模式：硬件复位或通过激活外部中断，当硬件复位退出掉电模式时，处理看门狗定时器可像通常的上电复位一样。当由中断退出掉电模式时则有所不同，中断低电平状态持续到晶体振荡稳定，当中断电平变为高电平事即可相应中断服务。以防止中断误复位，当器件复位，中断引脚持续为低时，看门狗定时器并未开始计数，知道中断引脚被拉高时为止。这为在掉电模式下的中断执行中断服务程序而设置。为保证看门狗定时器在退出掉电模式时极端情况下不溢出，最好在进入掉电模式前复位看门狗定时器。在进入空闲模式前，看门狗定时器打开时，WDT是否继续计数由SFR中的AUXR的WDIDLE位决定，在IDLE期间（位WDIDLE=0）默认状态是继续计数。为防止AT89S51从空闲模式中复位，用户应该周期性地设置定时器，重新进入空闲模式。
当WDIDLE位被置位，在空闲模式中看门狗定时器将停止计数，直到从空闲(IDLE)模式中退出重新开始计数。

目 录
第一章 项目总论 - 1 -
§1.1项目简介 - 1 -
§1.2可行性研究的范围 - 2 -
§1.3编制依据 - 2 -
第二章 项目建设背景及必要性 - 3 -
§2.1橡胶密封件项目提出的背景 - 3 -
§2.2国家产业政策 - 6 -
§2.3项目建设的必要性 - 8 -
第三章 项目优势 - 11 -
§3.1市场优势 - 11 -
§3.2技术优势 - 16 -
§3.3组织优势 - 17 -
§3.4政策优势:关中—天水经济区发展规划 - 17 -
§3.5区域投资环境优势 - 17 -
第四章 产品介绍与技术介绍 - 20 -
§4.1橡胶密封件产品介绍 - 20 -
§4.2 产品标准 - 21 -
§4.3 产品特征及材质 - 21 -
§4.4产品方案 - 26 -
§4.5产品技术来源 - 27 -
第五章 项目产品发展预测 - 28 -
§5.1产品行业关联环境分析 - 28 -
§5.2行业竞争格局与竞争行为 - 33 -
§5.3竞争力要素分析 - 39 -
§5.4项目发展预测 - 41 -
§5.5竞争结构分析及预测 - 43 -
第六章 项目产品规划 - 47 -
§6.1项目产品产能规划方案 - 47 -
§6.2产品工艺规划方案 - 47 -
§6.3项目产品营销规划方案 - 51 -
第七章 项目建设规划 - 58 -
§7.1项目建设总规 - 58 -
§7.2项目项目建设环境保护方案 - 61 -
§7.3项目建设节能方案 - 65 -
§7.4项目建设消防方案 - 66 -
§7.5项目建设生产劳动安全方案 - 69 -
第八章 项目组织实施情况 - 73 -
§8.1项目组织 - 73 -
§8.2项目劳动定员和人员培训 - 74 -
§8.3项目管理与实施进度安排 - 77 -
§8.4工程招标 - 80 -
第九章 项目财务评价分析 - 82 -
§9.1项目总投资及资金筹措 - 82 -
§9.2项目财务评价依据及相关说明 - 83 -
§9.3 项目总成本费用估算 - 84 -
§9.4 销售收入、销售税金及附加和增值税估算 - 84 -
§9.5 利润分配估算 - 85 -
§9.6 借款偿还计划 - 85 -
§9.7现金流估算 - 85 -
§9.8不确定性分析 - 86 -
§9.9风险分析 - 88 -
第十章 项目经济、社会效益评价 - 90 -
§10.1经济效益评价 - 90 -
§10.2社会效益评价 - 90 -
第十一章 可行性研究结论与建议 - 91 -
§11.1研究结论 - 91 -
§11.2建议 - 91 -